Thinfilm Company History

Thinfilm Addressable Memory

thinfilm_addressable_memory_prototypeTogether with PARC, a Xerox company, Thinfilm announced in October 2011 a working prototype of the world's first printed non-volatile memory device addressed with complementary organic circuits, the organic equivalent of CMOS circuitry. Thinfilm Addressable MemoryTM consists of Thinfilm's printed memory and PARC's transistors. This demonstration is a significant milestone toward the mass production of low-cost, low-power ubiquitous devices that are a key component of the "Internet of things."
Thinfilm Addressable Memory combines Thinfilm's polymer-based memory technology with PARC's transistor technology using complementary pairs of n-type and p-type transistors to construct the circuits. The addition of the integrated circuits makes the roll-to-roll printed Thinfilm Memory addressable by printable logic.

Printed Memories

In 2006, the first fully printed non-volatile re-writeable memory was demonstratedin collaboration with Xaar plc. The target was to print memories sufficient for storing 96 bit EPC codes.  The printed memory consisted of four fully printed layers: the ferroelectric polymer sandwiched between two PEDOT-PSS electrode layers and an optional contact pad layer. The layers were printed on industrial quality PET using standard ink-jet heads.  The memory displayed excellent characteristics such as cyclicity over 1 millionand10 years retention based on accelerated lifetime testing. The density of the memory elements was determined by the resolution of the print technique and the drive voltage was under 20 V.

 

 

TFT controlled memories

In parallel with the development of the hybrid memory technology Thinfilm also, together with a partner, developed TFT controlled 1 kbit passive array memory tags on plastic. The purpose was to demonstrate process compatibility as well as to investigate the suitability of using the TFTs for driving the passive array memory. The resulting 1 Kbit tags worked very well and TFT transistorswere able to construct adressing and read out logic for the passive memory array. Each tag was ca 5 by 5 mm in size, read out time was 50 µsec.

 

 

Hybrid memory development

Hybrid memory is defined as the combination of standard silicon control circuits in combination with separate layers of polymer memory. Together with Intel Corporation, TFE launched an extensive development program that demonstrated 512 Mb production ready hybrid passive array memory based on 0.25 µm technology. Each memory chip was based on 8 layers on top of the control circuitry. The chips without using error correction, demonstrating the world’s first working 3D passive array polymer memory technology

For its contributions to the development project, Intel received a minority shareholding in the company. As part of the same agreement Intel Corporation also acquired a non-exclusive license for certain applications of the hybrid memory technology.  The license agreement remains valid and in force.

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